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By Rajeev Alur; T A Henzinger; Stanford University. Computer Science Department

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During the message transmission phase, pc = send for the sender and pc = receive for the receiver. The sender takes an unknown number of rounds to transmit the message, asynchronously issuing an interface transmit event and simultaneously offering the message in the interface variable msg S . The receiver, ready to receive, sees the external transmit event and copies the message from the external variable msg S to the private variable msg R . During the message consumption phase, the receiver (pc = consume) takes an unknown number of rounds to consume the message.

19 shows a possible design of the three-bit counter from three onebit counters (for clarity, in Rml we can annotate the component modules of a compound module with the names of the observable variables even if the variables are not renamed). Note that carry 0 waits for both start and inc, then carry 1 waits for carry 0 , and carry 2 waits for carry 1 . It follows that all three bits of the counter are updated in a single round (clock cycle). 20 shows block diagrams for the one-bit counter Sync1BitCounter and the three-bit counter Sync3BitCounter .

17. Give a few initialized trajectories of the module SyncDelay. Then characterize, in precise words, the set of all initialized trajectories of SyncDelay. Is the module SyncDelay finite? Closed? Deterministic? 21: An initialized trajectory of the module Sync3BitCounter Reactive Modules 43 tic? Asynchronous? Passive? (d) Draw block diagrams for the module module SyncLatch2 is —interface out —external set, reset hide z1 , z2 , z3 in SyncNor [in 1 , in 2 , out := set, z3 , z1 ] SyncNor [in 1 , in 2 , out := reset, out, z2 ] SyncDelay[in, out := z1 , out] SyncDelay[in, out := z2 , z3 ] at three different levels of abstraction.

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A really temporal logic by Rajeev Alur; T A Henzinger; Stanford University. Computer Science Department


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