Get Advanced ASIC chip synthesis: using Synopsys Design PDF
By Himanshu Bhatnagar
Complicated ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment version describes the complicated suggestions and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the total ASIC layout move technique particular for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this ebook is on real-time software of Synopsys instruments, used to strive against a number of difficulties obvious at VDSM geometries. Readers may be uncovered to a good layout technique for dealing with advanced, sub-micron ASIC designs. importance is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT test insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties with regards to each one part of the layout stream are pointed out, with options and work-around defined intimately. moreover, the most important concerns regarding structure, consisting of clock tree synthesis and back-end integration (links to format) also are mentioned at size. moreover, the publication comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding types, distinct in the direction of optimum synthesis answer. goal audiences for this booklet are training ASIC layout engineers and masters point scholars project complicated VLSI classes on ASIC chip layout and DFT options.
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Extra info for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
Some layout tools provide direct interface to DC to perform this step. Chapter 9 introduces some of these steps, both traditional and not-so-traditional approaches. For the sake of simplicity, lets assume that the clock tree insertion to the original netlist has been performed. 12 Chapter 1 The layout tool generally performs routing in two phases – global routing and detailed routing. After placement, the design is globally routed to determine the quality of placement, and to provide estimated delays approximating the real delay values of the post-routed (after detailed routing) design.
In the pre-layout mode, PrimeTime uses the wire load models specified in the library to estimate the net delays. During this, the same timing constraints that were fed to DC previously are also fed to PrimeTime, specifying the relationship between the primary I/O signals and the clock. If the timing for all critical paths is acceptable, then a constraints file may be written out from PrimeTime or DC for the purpose of forward annotation to the layout tool. This constraint file in SDF format specifies the timing between each group of logic that the layout tool uses, in order to perform the timing driven placement of cells.
The clock tree insertion modifies the existing structure of the design. In other words, the netlist in the layout tool is different from the original netlist present in DC. This is because of the fact that the design present in the layout tool contains the clock tree, 32 Chapter 2 whereas the original design in DC does not contain this information. Therefore, the clock tree information should somehow be transferred to the design residing in DC or PT. The new netlist (containing the clock tree information) should be formally verified against the original netlist to ensure that the transfer of clock tree did not break the functionality of the original logic.
Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime by Himanshu Bhatnagar